In recent years, research and development are conducted on a nonvolatile memory device having memory cells that include variable resistance elements. A variable resistance element is an element that has a property that a resistance value changes (reversibly changes between a high resistance state and a low resistance state) according to an electrical signal and enables information to be written through this change in resistance value.
Exemplary structures for the memory cells using the variable resistance elements include a cross point structure as a structure suitable for high integration. In the cross point structure, each memory cell is placed at a different one of cross points of orthogonally arranged bit lines and word lines so as to be provided between a bit line and a word line. Various types of such cross point variable resistance nonvolatile memory devices are developed in recent years (see Patent Literatures (PTLs) 1 and 2, for instance).
PTL 1 discloses a nonvolatile memory device having memory cells that use bidirectional variable resistors in a cross point structure. With a view to reduce a so-called leakage current (leak current) flowing through unselected memory cells, PTL 1 discloses that, for example, a varistor is used as a bidirectional nonlinear element included in a memory cell, that writing to a selected memory cell is performed by applying a write voltage Vpp, Vss, and a voltage Vpp/2 to a selected bit line, a selected word line, and unselected word lines and unselected bit lines, respectively, at a time of writing, and that erasing of a selected memory cell is performed by applying a write voltage Vpp, Vss, and a voltage Vpp/2 to a selected word line, a selected bit line, and unselected word lines and unselected bit lines, respectively, at a time of erasing.
Similarly, PTL 2 discloses a nonvolatile memory device having a cross point memory cell array in which each memory cell including a bidirectional variable resistor and a bidirectional nonlinear element is placed at a different one of cross points of word lines arranged in parallel with each other and bit lines arranged orthogonal to the word lines, so as to form a matrix. PTL 2 discloses that the bidirectional nonlinear element is designed to reduce a leakage current that flows through unselected memory cells. Since, however, an amount of leakage current depends on an array size of a memory cell array, an increase in array size causes a significant increase in leakage current. In response to such a problem, PTL 2 discloses, as a method of reducing a leakage current, a means for applying a predetermined voltage to an unselected word line and an unselected bit line, thereby enabling more stable reading.